The present invention relates to a semiconductor device and method of manufacturing the same and, more specifically, to a structure and method for manufacturing a hybrid crystalline orientation complementary metal-oxide-semiconductor (CMOS) with an ultra-thin-silicon-on-insulator (UT-SOI) at the tip of a V-shape channel.
Mobility of electrons or holes depends on surface crystalline orientations in silicon. In a metal-oxide-semiconductor field-effect transistor (MOSFET) with an n-type channel (nMOSFET), electrons are responsible for conduction. In a MOSFET with a p-type channel (pMOSFET), holes are responsible for conduction. It is desirable to build an nMOSFET in a (100) surface and a pMOSFET in a (111) surface in order to obtain the maximum electron mobility for the nMOSFET and the maximum hole mobility for the pMOSFET.
Conventional hybrid-orientation technology (HOT) requires selective epitaxial growth of silicon which can generate dislocations and reduce yield.
UT-SOI has a better short channel effect than partially depleted silicon-on-insulator (SOI) and/or bulk MOSFETs. However, UT-SOI degrades mobility which then reduces device performance.